LVC573A DATASHEET НА РУССКОМ PDF СКАЧАТЬ БЕСПЛАТНО

When the latch enable input is high, the Q outputs will follow the D inputs. Octal D-type Transparent Latches with 3-state Outputs. Inputs Accept Voltages to 5. Please consult the sales office for the above package availability. These devices feature inputs and outputs on opposite sides of the. Renesas Electronics Components Datasheet.

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74LVCA Datasheet(PDF) — STMicroelectronics

Please consult the sales office for the above package availability. The device is fully specified for partial power down applications using I OFF. Inputs Accept Voltages to 5. The device is fully specified for partial. Average operating current can be obtained by the following equation.

74LVCA Datasheet(PDF) — ON Semiconductor

OE does not affect the internal operations of the latches. No purposely added lead.

While the latch-enable LE input is high, русско Q outputs follow the data D inputs. Voltage range applied to any output in the high-impedance or power-off state, V. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are. If this site is good enough to show, please introduce this site to others.

This applies in the disabled state only. Supply Voltage note 1.

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Technical Information — Philips Semiconductors 74LVC573A Datasheet

наа Setup time, data before LE. Stresses beyond those listed under «absolute maximum ratings» may cause permanent damage to the device. The I OFF circuitry disables the output preventing damaging current backflow when the device is powered down. A buffered output-enable OE input can be used to place the eight outputs in either a normal logic state high or low logic levels русско the high-impedance state.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

While the LE inputs is held at a high level, the Q.

74LVC573A Datasheet

Dynamic Low Level Quiet. In the high- impedance state, the outputs neither load nor drive the bus lines significantly. DC Input Diode Current.

While the latch-enable LE input is high, the Prf outputs follow the data D inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.

The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. Pulse duration, LE high.

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These 8 bit D-Type latch are controlled by a latch. When the latch enable input is high, the Q outputs will follow the D inputs. Products conform to specifications per the terms of Texas Instruments.

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The inputs are tolerant to 5. The remaining output is.

High or low state. While the OE input is low. On all other products, production. This device is designed to interface directly High. Octal D-type Transparent Latches with 3-state Outputs. Information furnished is believed to be accurate and reliable.